The invention relates to electronic switches. More particularly, the invention relates to a method and system for switching signals according to a control voltage and having impedance matching means.
Semiconductor devices are typically used in a wide variety of electronic switching circuit applications that require high speed switching, such as RF and microwave switching applications. For example, a Field Effect Transistor (FET) is often used as a single switch in a switching circuit. An FET includes a drain terminal, a source terminal, and a gate terminal, with current being switched between the drain and source terminal according to a control signal applied to the gate terminal.
FIG. 1 illustrates an example of a conventional switching circuit, as described in U.S. Pat. No. 5,767,721, in a single pole, single throw (SPST) switch circuit configuration utilizing two depletion-mode FETs. Referring to FIG. 1, a series FET 100 is coupled between an input terminal 10 and an output terminal 20 to allow signals to be transferred between the terminals 10, 20 when turned on and block such transmission when turned off. Respective coupling capacitors 30, 40 are interposed between each terminal 10, 20 and the series FET 100 to block DC voltages while admitting AC signals with little or no attenuation. The drain terminal 101 and source terminal 102 of the series FET 100 are each coupled to a predetermined positive potential V+ by respective biasing resistors 50, 60. The gate terminal 103 of the series FET 100 is coupled to the control voltage V1 via a gate resistor 70. Biasing the series FET 100 in this manner enables it to be turned off when V1 is at a zero potential.
The circuit also includes a shunt FET 150 coupled to the series FET 100 in a shunt configuration. In particular, the drain terminal 151 of the shunt FET 150 is coupled to the source terminal 102 of the series FET 100 through a third coupling capacitor 80, which is also utilized to block DC signals. The source terminal 152 of the shunt FET 150 is coupled to ground via a fourth coupling capacitor 85. The gate terminal 153 of the shunt FET 150 is also coupled to ground via a second gate resistor 82.
The drain terminal 151 and source terminal 152 of the shunt FET 150 are also coupled to the control voltage V1 by respective high value biasing resistors 90, 95. Biasing the shunt FET 150 in this manner enables it to be turned on when V1 is at a zero voltage and turned off when V1 is at a significant positive voltage.
In operation, the switch circuit of FIG. 1 operates in either an “on” or “off” mode. When the control voltage V1 transitions from a zero to a positive potential, the switch circuit enters the on mode, which causes the series FET 100 to be turned on while simultaneously turning off the shunt FET 150. In this mode, the series FET 100 allows signals to be transmitted between the input and output terminals 10, 20 while the shunt FET 150 does not pass any significant current.
In contrast, while in the off mode, i.e., when the control voltage V1 transitions to back a zero potential, the series FET 100 is turned off and the shunt FET 150 is turned on. Since the series FET 100 is off, signals are effectively blocked from being transmitted between the terminals 10, 20. Meanwhile, the shunt FET 150 is on, which provides a low impedance path to ground at the output terminal 20 for input isolation purposes.
There are, however, limitations in the prior art systems. Particularly, in the off mode, a highly reflective load impedance is connected to the input of the switch, which effectively reflects RF signals input to the switch back to the source. This configuration provides isolation at the input of the switch, i.e., from input to output, but offers limited isolation for signal sources common to the output, i.e., from output to input.